1. Field of the Invention
The invention relates to resetting of digital circuit, and more particularly to integrated circuits generating self-timed resets upon power start-up.
2. Description of the Related Art
Digital circuits require a start-up reset in order to set a system to a know initial state. Conventional power-detection circuits for generating the reset signal use large value discrete resistors and capacitors which is not area-efficient in integrated circuits. In addition, power consumption is higher than desired and an external reset pin and extra external discrete components complicate the design.
Three U.S. Patents are known which deal with power-on reset circuits. U.S. Pat. No. 5,343,085 (Fujimoro, et al.) discloses a power-on reset circuit for an integrated circuit having a pulse generator, an oscillator, and a counter for creating a relatively long reset period. The pulse generator, however, appears to use a discrete resistor and capacitor. U.S. Pat. No. 5,148,051 (Deierling et al.) provides a power up circuit for an IC which separately tests the voltage level and delays the power-up reset, but differs from the present invention in that duration of the power-up reset depends mainly on a string of circuit delays. U.S. Pat. No. 4,900,950 (Dubujet) describes a power-on reset circuit having an oscillator, but the oscillator is used to provide a voltage higher than the supply voltage and application of power is delayed until the supply voltage has reached an acceptable value.